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| STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features Core: ARM 32-bit CortexTM-M3 CPU - 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 64 or 128 Kbytes of Flash memory - 20 Kbytes of SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC - PLL for CPU clock - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers 2 x 12-bit, 1 s A/D converters (up to 16 channels) - Conversion range: 0 to 3.6 V - Dual-sample and hold capability - Temperature sensor DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs Up to 80 fast I/O ports - 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant VFQFPN36 6 x 6 mm LQFP100 14 x 14 m LQFP64 10 x 10 m LQFP48 7 x 7 m BGA100 10 x 10 mm BGA64 5 x 5 mm Debug mode - Serial wire debug (SWD) & JTAG interfaces 7 timers - Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 16-bit, motor control PWM timer with deadtime generation and emergency stop - 2 watchdog timers (Independent and Window) - SysTick timer: a 24-bit downcounter Up to 9 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (18 Mbit/s) - CAN interface (2.0B Active) - USB 2.0 full-speed interface CRC calculation unit, 96-bit unique ID Packages are ECOPACK(R) Device summary Part number STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103RB STM32F103VB, STM32F103CB Table 1. Reference STM32F103x8 STM32F103xB September 2009 Doc ID 13587 Rev 11 1/92 www.st.com 1 Contents STM32F103x8, STM32F103xB Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 12 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Universal synchronous/asynchronous receiver transmitter (USART) . . 17 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 18 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Contents 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics . . . . . . . . . . . 36 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 56 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 67 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 83 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Doc ID 13587 Rev 11 3/92 Contents STM32F103x8, STM32F103xB 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 41 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 42 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Doc ID 13587 Rev 11 5/92 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. STM32F103x8, STM32F103xB ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 74 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 77 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 78 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 79 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 81 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM32F103xx Performance Line VFQFPN36 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 40 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 40 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 71 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 72 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 76 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 77 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 78 Doc ID 13587 Rev 11 7/92 List of figures Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM32F103x8, STM32F103xB Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 79 Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 80 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 81 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F103x8 and STM32F103xB performance line family incorporates the highperformance ARM CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx medium-density performance line family operates from a 2.0 to 3.6 V power supply. It is available in both the -40 to +85 C temperature range and the -40 to +105 C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications: Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. Doc ID 13587 Rev 11 9/92 Description STM32F103x8, STM32F103xB 2.1 Device overview Table 2. STM32F103xx medium-density device features and peripheral counts STM32F103Tx 64 20 3 1 1 1 2 1 1 26 2 10 channels 2 2 3 1 1 37 2 10 channels STM32F103Cx 64 20 3 1 2 2 3 1 1 128 20 3 STM32F103Rx 64 20 3 1 2 2 3 1 1 51 2 16 channels 128 STM32F103Vx 64 20 3 1 2 2 3 1 1 80 2 16 channels 128 Peripheral Flash - Kbytes SRAM - Kbytes Timers Communication General-purpose Advanced-control SPI I2C USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage Operating temperatures Packages 72 MHz 2.0 to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C (see Table 9) Junction temperature: -40 to + 125 C (see Table 9) VFQFPN36 LQFP48 LQFP64, TFBGA64 LQFP100, LFBGA100 10/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Description 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 100 64 48 36 2 x USARTs 2 x 16-bit timers 1 x SPI, 1 x I2C, USB, CAN, 1 x PWM timer 2 x ADCs 3 x USARTs 3 x 16-bit timers 2 x SPIs, 2 x I2Cs, USB, CAN, 1 x PWM timer 2 x ADCs 5 x USARTs 4 x 16-bit timers, 2 x basic timers 3 x SPIs, 2 x I2Ss, 2 x I2Cs USB, CAN, 2 x PWM timers 3 x ADCs, 2 x DACs, 1 x SDIO FSMC (100 and 144 pins) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. Doc ID 13587 Rev 11 11/92 Description STM32F103x8, STM32F103xB 2.3 2.3.1 Overview ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead 12/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Description This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.3.9 Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains Doc ID 13587 Rev 11 13/92 Description STM32F103x8, STM32F103xB in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 14/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Description 2.3.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Timers and watchdogs The medium-density STM32F103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4. Timer Timer feature comparison Counter resolution 16-bit Counter type Up, down, up/down Up, down, up/down Prescaler factor Any integer between 1 and 65536 Any integer between 1 and 65536 DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes TIM1 TIM2, TIM3, TIM4 16-bit Yes 4 No Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It Doc ID 13587 Rev 11 15/92 Description STM32F103x8, STM32F103xB can also be seen as a complete general-purpose timer. The 4 independent channels can be used for Input capture Output compare PWM generation (edge- or center-aligned modes) One-pulse mode output If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 16/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Description SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source 2.3.16 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 2.3.18 Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 2.3.19 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 2.3.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). Doc ID 13587 Rev 11 17/92 Description STM32F103x8, STM32F103xB 2.3.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 18/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 1. TRACECLK TRACED[0:3] as AS Description STM32F103xx performance line block diagram TPIU SW/JTAG Trace/trig pbu s Ibus Trace Controlle r flash obl Inte rfac e POWER VOLT. REG. 3.3V TO 1.8V @VDD NJTRST TRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF VDD = 2 to 3.6V VSS Cortex-M3 CPU Fmax : 7 2M Hz Dbus Flash 128 KB 64 bit BusM atrix NVIC Syst em SRAM 20 KB PCLK1 PCLK2 HCLK FCLK RC 8 MHz RC 40 kHz @VDDA @VBAT PLL & CLOCK MANAGT @VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT GP DMA AHB:F max =48/72 MHz 7 ch annels IWDG Stand by in terface @VDDA SUPPLY SUPERVISION POR / PDR PVD 80AF PA[ 15:0] PB[ 15:0] PC[15:0] PD[15:0] PE[15:0] EXTI WAKEUP GPIOA GPIOB GPIOC GPIOD GPIOE APB2 : F max =48 / 72 MHz Rst Int VBAT OSC32_IN OSC32_OUT TAMPER-RTC NRST VDDA VSSA XTAL 32 kHz AHB2 APB2 AHB2 APB 1 RTC AWU Back up reg Backu p i nterf ace TIM2 TIM3 APB1 : Fmax =24 / 36 MHz TIM 4 USART2 USART3 SPI2 2x(8x16bit) I2C1 I2C2 bx CAN USB 2.0 FS 4 Chann els 4 Chann els 4 Chann els RX,TX, CTS, RTS, CK, SmartCard as AF RX,TX, CTS, RTS, CK, SmartCard as AF MOSI,MISO,SCK,NSS as AF SCL,SDA,SMBA as AF SCL,SDA as AF USBDP/CAN_TX USBDM/CAN_RX 4 Chann els 3 co mpl. Chann els ETR and BKIN MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, Smart Card as AF TIM1 SPI1 USART1 @VDDA 16AF VREF+ VREF- 12bit ADC1 IF SRAM 512B 12bi t ADC2 IF WWDG Temp sensor ai14390d 1. TA = -40 C to +105 C (junction temperature up to 125 C). 2. AF = alternate function on I/O port pin. Doc ID 13587 Rev 11 19/92 Description Figure 2. Clock tree 8 MHz HSI RC HSI STM32F103x8, STM32F103xB /2 USB Prescaler /1, 1.5 48 MHz USBCLK to USB interface HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock Enable (13 bits) 72 MHz max Clock Enable (3 bits) PLLSRC PLLMUL ..., x16 x2, x3, x4 PLL HSI PLLCLK HSE SW SYSCLK /8 72 MHz /1, 2..512 max AHB Prescaler APB1 Prescaler /1, 2, 4, 8, 16 36 MHz max CSS to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock Enable (3 bits) PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 APB2 Prescaler /1, 2, 4, 8, 16 72 MHz max Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock LSE to RTC /128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz ADC Prescaler /2, 4, 6, 8 Enable (1 bit) to ADC RTCCLK RTCSEL[1:0] ADCCLK LSI RC 40 kHz LSI to Independent Watchdog (IWDG) IWDGCLK Legend: Main Clock Output /2 PLLCLK HSI HSE SYSCLK MCO HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal MCO ai14903 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz. 20/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Pinouts and pin description 3 Figure 3. 1 Pinouts and pin description STM32F103xx performance line LFBGA100 ballout 2 3 4 5 6 7 8 9 10 A PC14PC13OSC32_IN TAMPER-RTC PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF- PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI16001c Doc ID 13587 Rev 11 21/92 Pinouts and pin description Figure 4. STM32F103x8, STM32F103xB STM32F103xx performance line LQFP100 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14391 22/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 5. Pinouts and pin description STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 Doc ID 13587 Rev 11 23/92 Pinouts and pin description Figure 6. STM32F103x8, STM32F103xB STM32F103xx performance line TFBGA64 ballout 1 2 3 4 5 6 7 8 A PC14PC13OSC32_IN TAMPER-RTC PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12 C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 24/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 7. Pinouts and pin description STM32F103xx performance line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14393b Figure 8. STM32F103xx Performance Line VFQFPN36 pinout BOOT0 VSS_3 PA15 PA14 PB7 PB6 PB5 PB4 PB3 36 VDD_3 OSC_IN/PD0 OSC_OUT/PD1 NRST VSSA VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 35 34 33 32 31 30 29 28 27 26 25 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 VDD_1 QFN36 23 22 21 20 19 18 11 12 13 14 15 16 17 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 VSS_1 ai14654 Doc ID 13587 Rev 11 25/92 Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions I / O Level(2) Pins VFQFPN36 LFBGA100 TFBGA64 LQFP100 LQFP48 LQFP64 Pin name Type(1) STM32F103x8, STM32F103xB Alternate functions(4) Main function(3) (after reset) Default Remap A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2 E2 F3 G1 H1 J1 K1 1 2 3 4 5 6 7 8 9 B2 A2 A1 B1 C1 D1 E1 E3 E2 F2 -(7) F1 G1 (7) 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 5 6 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(5) I/O FT I/O FT I/O FT I/O FT I/O FT S I/O PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) PC14(6) PC15(6) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA TRACECK TRACED0 TRACED1 TRACED2 TRACED3 TAMPER-RTC OSC32_IN OSC32_OUT PC14-OSC32_IN(5) I/O PC15OSC32_OUT(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA I/O S S I O I/O I/O I/O I/O I/O S S S S ADC12_IN10 ADC12_IN11 ADC12_IN12 ADC12_IN13 H1 G2 10 G2 14 23 7 PA0-WKUP I/O PA0 WKUP/ USART2_CTS(8)/ ADC12_IN0/ TIM2_CH1_ETR(8) USART2_RTS(8)/ ADC12_IN1/ TIM2_CH2(8) USART2_TX(8)/ ADC12_IN2/ TIM2_CH3(8) H2 11 H2 15 24 8 PA1 I/O PA1 J2 12 F3 16 25 9 PA2 I/O PA2 26/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 5. Pinouts and pin description Medium-density STM32F103xx pin definitions (continued) I / O Level(2) Pins VFQFPN36 Alternate functions(4) Main function(3) (after reset) Type(1) LFBGA100 TFBGA64 LQFP100 LQFP48 LQFP64 Pin name Default USART2_RX(8)/ ADC12_IN3/ TIM2_CH4(8) Remap K2 E4 F4 G3 13 14 G3 C2 D2 H3 17 18 19 20 26 27 28 29 10 11 PA3 VSS_4 VDD_4 PA4 I/O S S I/O PA3 VSS_4 VDD_4 PA4 SPI1_NSS(8)/ USART2_CK(8)/ ADC12_IN4 SPI1_SCK(8)/ ADC12_IN5 SPI1_MISO(8)/ ADC12_IN6/ TIM3_CH1(8) SPI1_MOSI(8)/ ADC12_IN7/ TIM3_CH2(8) ADC12_IN14 ADC12_IN15 ADC12_IN8/ TIM3_CH3(8) ADC12_IN9/ TIM3_CH4(8) TIM1_CH2N TIM1_CH3N TIM1_BKIN H3 15 F4 21 30 12 PA5 I/O PA5 J3 16 G4 22 31 13 PA6 I/O PA6 K3 G4 H4 J4 K4 G5 H5 J5 K5 G6 H6 J6 K6 G7 H7 J7 K7 E7 17 18 19 20 21 22 23 H4 H5 H6 F5 G5 G6 G7 H7 D6 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 14 PA7 PC4 PC5 I/O I/O I/O I/O I/O PA7 PC4 PC5 PB0 PB1 TIM1_CH1N 15 16 17 18 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 I/O FT PB2/BOOT1 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 I2C2_SCL/ USART3_TX(8) I2C2_SDA/ USART3_RX(8) TIM1_ETR TIM1_CH1N TIM1_CH1 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4 Doc ID 13587 Rev 11 27/92 Pinouts and pin description Table 5. STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) I / O Level(2) Pins VFQFPN36 Alternate functions(4) Main function(3) (after reset) Type(1) LFBGA100 TFBGA64 LQFP100 LQFP48 LQFP64 Pin name Default Remap F7 24 E6 32 50 19 VDD_1 S VDD_1 SPI2_NSS/ I2C2_SMBAl/ USART3_CK(8)/ TIM1_BKIN(8) SPI2_SCK/ USART3_CTS(8)/ TIM1_CH1N (8) SPI2_MISO/ USART3_RTS(8) TIM1_CH2N (8) SPI2_MOSI/ TIM1_CH3N(8) USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 USART1_CK/ TIM1_CH1(8)/MCO USART1_TX(8)/ TIM1_CH2(8) USART1_RX(8)/ TIM1_CH3(8) USART1_CTS/ CANRX(8)/ USBDM TIM1_CH4(8) USART1_RTS/ CANTX(8) //USBDP TIM1_ETR(8) K8 25 H8 33 51 - PB12 I/O FT PB12 J8 26 G8 34 52 - PB13 I/O FT PB13 H8 27 F8 35 53 - PB14 I/O FT PB14 G8 K9 J9 H9 G9 K10 J10 H10 G10 F10 E10 F9 E9 D9 C9 28 - F7 F6 E7 E8 36 37 38 39 40 41 42 43 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 20 21 22 PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 29 30 D8 D7 C7 C6 D10 31 C10 32 C8 44 70 23 PA11 I/O FT PA11 B10 33 B8 45 71 24 PA12 I/O FT PA12 28/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 5. Pinouts and pin description Medium-density STM32F103xx pin definitions (continued) I / O Level(2) Pins VFQFPN36 Alternate functions(4) Main function(3) (after reset) Type(1) LFBGA100 TFBGA64 LQFP100 LQFP48 LQFP64 Pin name Default Remap A10 34 F8 E6 F6 A9 A8 B9 B8 C8 D8 E8 B7 C7 D7 B6 C6 D6 A7 39 35 36 37 38 5 6 A8 D5 E5 A7 A6 B7 B6 C5 C1 D1 B5 A5 46 47 48 49 50 51 52 53 5 6 54 55 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 25 26 27 28 29 PA13 I/O FT JTMS/SWDIO Not connected PA13 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 S S VSS_2 VDD_2 PA14 TIM2_CH1_ETR/ PA15 /SPI1_NSS USART3_TX USART3_RX USART3_CK CANRX CANTX TIM3_ETR USART2_CTS USART2_RTS USART2_TX USART2_RX USART2_CK TIM2_CH2 / PB3 TRACESWO SPI1_SCK TIM3_CH1/ PB4/ SPI1_MISO I/O FT JTCK/SWCLK I/O FT I/O FT I/O FT I/O FT I/O FT JTDI PC10 PC11 PC12 OSC_IN(9) 2 3 30 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 I/O FT OSC_OUT(9) I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PD2 PD3 PD4 PD5 PD6 PD7 JTDO A6 40 A4 56 90 31 PB4 I/O FT JNTRST C5 B5 A5 D5 B4 A4 41 42 43 44 45 46 C4 D3 C3 B4 B3 A3 57 58 59 60 61 62 91 92 93 94 95 96 32 33 34 35 - PB5 PB6 PB7 BOOT0 PB8 PB9 I/O I/O FT I/O FT I I/O FT I/O FT PB5 PB6 PB7 BOOT0 PB8 PB9 I2C1_SMBAl I2C1_SCL(8)/ TIM4_CH1(8) I2C1_SDA(8)/ TIM4_CH2(8) TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX TIM4_CH3(8) TIM4_CH4(8) I2C1_SCL / CANRX I2C1_SDA/ CANTX Doc ID 13587 Rev 11 29/92 Pinouts and pin description Table 5. STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) I / O Level(2) Pins VFQFPN36 Alternate functions(4) Main function(3) (after reset) Type(1) LFBGA100 TFBGA64 LQFP100 LQFP48 LQFP64 Pin name Default Remap D4 C4 E5 F5 47 48 D4 E4 63 64 97 98 99 100 36 1 PE0 PE1 VSS_3 VDD_3 I/O FT I/O FT S S PE0 PE1 VSS_3 VDD_3 TIM4_ETR 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 10. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 30/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Memory mapping 4 Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map APB memory space 0xFFFF FFFF reserved 0xE010 0000 0xFFFF FFFF reserved 0x6000 0000 reserved 0x4002 3400 7 0xE010 0000 0xE000 0000 Cortex- M3 Internal Peripherals CRC 0x4002 3000 reserved 0x4002 2400 Flash Interface 0x4002 2000 reserved 0x4002 1400 0x4002 1000 RCC reserved 6 0xC000 0000 0x4002 0400 DMA 0x4002 0000 reserved 0x4001 3C00 0x4001 3800 0x4001 3400 USART1 reserved SPI1 5 0xA000 0000 0x4001 3000 TIM1 0x4001 2C00 ADC2 0x4001 2800 ADC1 0x4001 2400 4 0x8000 0000 rese rve d 0x1FFF FFFF 0x4001 1C00 rese rved 0x1FFF F80F Option Bytes 0x1FFF F800 Por t E 0x4001 1800 Port D 0x4001 1400 Port C 0x4001 1000 Port B 0x4001 0C00 3 0x1FFF F000 0x6000 0000 System memory Port A 0x4001 0800 EXTI 0x4001 0400 AFIO 0x4001 0000 reserved 0x4000 7400 PWR BKP 2 rese rved 0x4000 0000 Peripherals 0x4000 7000 0x4000 6C00 reserved 0x4000 6800 0x4000 6400 0x4000 6000 bxCAN shared 512 byte USB/CAN SRAM USB Reg isters 1 0x2000 0000 SRAM 0x0801 FFFF 0x4000 5C00 I2C2 0x4000 5800 I2C1 0x4000 5400 reserved 0x4000 4C00 USART3 0x4000 4800 USART2 0 0x0000 0000 0x0800 0000 0x4000 4400 Flash memory reserved 0x4000 3C00 SPI2 0x4000 3800 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins reserved 0x4000 3400 IWDG 0x4000 3000 WWDG 0x4000 2C00 RTC 0x4000 2800 Reserved reserved 0x4000 0C00 TIM4 0x4000 0800 0x4000 0400 0x4000 0000 TIM3 TIM2 ai14394f Doc ID 13587 Rev 11 31/92 Electrical characteristics STM32F103x8, STM32F103xB 5 5.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. 32/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics Figure 10. Pin loading conditions Figure 11. Pin input voltage STM32F103xx pin C = 50 pF VIN STM32F103xx pin ai14141 ai14142 5.1.6 Power supply scheme Figure 12. Power supply scheme VBAT 1.8-3.6V Po wer swi tch Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 VSS Regulator 5 x 100 nF + 1 x 4.7 F VDD VREF 1/2/3/4/5 VDDA VREF+ VREFVSSA ai14125d 10 nF + 1 F 10 nF + 1 F ADC Analog: RCs, PLL, ... Caution: In Figure 12, the 4.7 F capacitor must be connected to VDD3. Doc ID 13587 Rev 11 33/92 Electrical characteristics STM32F103x8, STM32F103xB 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD-VSS VIN |VDDx| |VSSX VSS| VESD(HBM) Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min -0.3 VSS 0.3 VSS 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS. 34/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 7. Symbol IVDD IVSS IIO Electrical characteristics Current characteristics Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink) (1) Max. 150 150 25 25 Unit Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) IINJ(PIN)(2) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin (4) mA 5 5 5 25 Total injected current (sum of all I/O and control pins)(4) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 8. Thermal characteristics Ratings Storage temperature range Maximum junction temperature Value -65 to +150 150 Unit C C Symbol TSTG TJ 5.3 5.3.1 Operating conditions General operating conditions Table 9. Symbol fHCLK fPCLK1 fPCLK2 VDD General operating conditions Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage Conditions Min 0 0 0 2 2 Must be the same potential as VDD(2) 2.4 1.8 Max 72 36 72 3.6 3.6 V 3.6 3.6 V V MHz Unit VDDA(1) VBAT Doc ID 13587 Rev 11 35/92 Electrical characteristics Table 9. Symbol STM32F103x8, STM32F103xB General operating conditions (continued) Parameter Conditions LFBGA100 LQFP100 Min Max 454 434 308 mW 444 363 1110 -40 -40 -40 -40 -40 -40 85 C 105 105 C 125 105 C 7 suffix version 125 Unit PD Power dissipation at TA = 85 C TFBGA64 for suffix 6 or TA = 105 C for LQFP64 suffix 7(3) LQFP48 VFQFPN36 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation (4) TA Ambient temperature for 7 suffix version TJ Junction temperature range Maximum power dissipation Low power dissipation(4) 6 suffix version 1. When the ADC is used, refer to Table 45: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 82). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 82). 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Symbol tVDD Operating conditions at power-up / power-down Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit s/V 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 36/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 11. Symbol Electrical characteristics Embedded reset and power control block characteristics Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms VPVD Programmable voltage detector level selection PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge) VPVDhyst (2) PVD hysteresis Power on/power down reset threshold PDR hysteresis VPOR/PDR VPDRhyst (2) TRSTTEMPO(2) Reset temporization 2. Guaranteed by design, not tested in production. 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. Doc ID 13587 Rev 11 37/92 Electrical characteristics STM32F103x8, STM32F103xB 5.3.4 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions -40 C < TA < +105 C -40 C < TA < +85 C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V s ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V 10 mV 10 100 mV ppm/C 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 38/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 13. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Parameter Conditions fHCLK TA = 85 C 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz 50 36.1 28.6 19.9 14.7 8.6 32.8 24.4 19.8 13.9 10.7 6.8 TA = 105 C 50.3 36.2 28.7 20.1 14.9 8.9 mA 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 32.9 24.5 19.9 14.2 11 7.1 Unit Symbol IDD Supply current in Run mode 8 MHz 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 48 31.5 24 17.5 12.5 7.5 29 20.5 16 11.5 8.5 5.5 TA = 105 C 50 32 25.5 18 13 8 29.5 21 16.5 12 9 6 mA Symbol IDD Supply current in Run mode 8 MHz 72 MHz 48 MHz External clock(2), all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 11 39/92 Electrical characteristics STM32F103x8, STM32F103xB Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 35 Consumption (mA) 30 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (C) 72 MHz 36 MHz 16 MHz 8 MHz Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 30 25 Consumption (mA) 20 72 MHz 36 MHz 16 MHz 8 MHz 15 10 5 0 -40 0 25 70 85 105 Temperature (C) 40/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 15. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2), all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 C 30 20 15.5 11.5 8.5 5.5 7.5 6 5 4.5 4 3 TA = 105 C 32 20.5 16 12 9 6 8 6.5 5.5 5 4.5 4 mA Symbol IDD Supply current in Sleep mode 8 MHz 72 MHz 48 MHz External clock(2), all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz 1. based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 11 41/92 Electrical characteristics Table 16. Symbol STM32F103x8, STM32F103xB Typical and maximum current consumptions in Stop and Standby modes Typ(1) Parameter Conditions Max VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current 1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production. - 23.5 24 200 370 - 13.5 14 180 340 IDD - 2.6 2.4 3.4 3.2 - - A - 1.7 2 4 5 0.9 1.1 1.4 1.9(2) 2.2 Figure 16. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values 2.5 Consumption ( A ) 2 1.5 1 0.5 0 -40 C 25 C 70 C Temperature (C) ai17351 2V 2.4 V 3V 3.6 V 85 C 105 C 42/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics Figure 17. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V 300 250 Consumption (A) 200 150 100 50 0 -45 25 70 Temperature (C) 90 110 3.3 V 3.6 V Figure 18. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 300 250 Consumption (A) 200 150 100 50 0 -40 0 25 70 85 105 Temperature (C) 3.3 V 3.6 V Doc ID 13587 Rev 11 43/92 Electrical characteristics STM32F103x8, STM32F103xB Figure 19. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 3.5 Consumption (A) 3 2.5 2 1.5 1 0.5 0 -45 C 25 C 85 C 105 C Temperature (C) 3.3 V 3.6 V Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 44/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 17. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Parameter Conditions fHCLK Unit Symbol All peripherals All peripherals disabled enabled(2) 36 24.2 19 12.9 9.3 5.5 3.3 2.2 1.6 1.3 1.08 31.4 23.5 18.3 12.2 8.5 4.9 2.7 1.6 1.02 0.73 0.5 27 18.6 14.8 10.1 7.4 4.6 2.8 1.9 1.45 1.25 1.06 23.9 17.9 14.1 9.5 6.8 4 2.2 1.4 0.9 0.67 0.48 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz mA IDD Supply current in Run mode 125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 13587 Rev 11 45/92 Electrical characteristics Table 18. STM32F103x8, STM32F103xB Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 14.4 9.9 7.6 5.3 3.8 2.1 1.6 1.3 1.11 1.04 0.98 12.3 9.3 7 4.8 3.2 1.6 1 0.72 0.56 0.49 0.43 5.5 3.9 3.1 2.3 1.8 1.2 1.1 1 0.98 0.96 0.95 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz mA 4.4 3.3 2.5 1.8 1.2 0.6 0.5 0.47 0.44 0.42 0.41 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 46/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - - with all peripherals clocked off with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Peripheral current consumption(1) Peripheral TIM2 TIM3 TIM4 SPI2 USART2 Table 19. Typical consumption at 25 C 1.2 1.2 0.9 0.2 0.35 Unit APB1 USART3 I2C1 I2C2 USB CAN GPIO A GPIO B GPIO C GPIO D GPIO E APB2 ADC1(2) ADC2 TIM1 SPI1 USART1 0.35 0.39 0.39 0.65 0.72 0.47 0.47 0.47 0.47 0.47 mA mA 1.81 1.78 1.6 0.43 0.85 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. Doc ID 13587 Rev 11 47/92 Electrical characteristics STM32F103x8, STM32F103xB 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) High-speed external user clock characteristics Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 45 VSS VIN VDD 5 55 1 Conditions Min 1 0.7VDD VSS 16 ns 20 pF % A Typ 8 Max 25 VDD 0.3VDD Unit MHz V DuCy(HSE) Duty cycle IL OSC_IN Input leakage current 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) Low-speed external user clock characteristics Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) OSC32_IN input capacitance(1) 30 VSS VIN VDD 5 70 1 0.7VDD VSS 450 ns 50 pF % A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current 1. Guaranteed by design, not tested in production. 48/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics Figure 20. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 21. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t EXTER NAL CLOCK SOURC E fLSE_ext OSC32_IN IL STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 13587 Rev 11 49/92 Electrical characteristics Table 22. Symbol fOSC_IN RF C STM32F103x8, STM32F103xB HSE 4-16 MHz oscillator characteristics(1) (2) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance RS = 30 VDD = 3.3 V, VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF i2 gm tSU(HSE (4) 1 mA mA/V ms startup time 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx fHSE CL2 ai14145 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 50/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 23. Symbol RF C(2) I2 gm tSU(LSE)(4) Electrical characteristics LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator Transconductance startup time VDD is stabilized RS = 30 k VDD = 3.3 V, VIN = VSS 5 3 Conditions Min Typ 5 15 1.4 Max Unit M pF A A/V s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 23. Typical application with a 32.768 kHz crystal Caution: Resonator with integrated capacitors CL1 OSC32_IN 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Doc ID 13587 Rev 11 51/92 Electrical characteristics STM32F103x8, STM32F103xB High-speed internal (HSI) RC oscillator Table 24. Symbol fHSI HSI oscillator characteristics(1) Parameter Frequency User-trimmed with the RCC_CR register(2) Conditions Min Typ 8 1(3) -2 -1.5 -1.3 -1.1 1 80 2.5 2.2 2 1.8 2 100 Max Unit MHz % % % % % s A ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) TA = -40 to 105 C TA = -10 to 85 C TA = 0 to 70 C TA = 25 C tsu(HSI)(4) IDD(HSI)(4) HSI oscillator startup time HSI oscillator power consumption 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator Table 25. Symbol fLSI(2) tsu(LSI) (3) LSI oscillator characteristics (1) Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.65 Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A IDD(LSI)(3) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 52/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 26. Low-power mode wakeup timings Parameter Wakeup from Sleep mode Electrical characteristics Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Typ 1.8 3.6 Unit s Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low power mode) Wakeup from Standby mode s 5.4 50 s 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. Symbol PLL characteristics Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8.0 Max(1) 25 60 72 200 300 Unit MHz % MHz s ps fPLL_IN fPLL_OUT tLOCK Jitter PLL input clock duty cycle PLL multiplier output clock PLL lock time Cycle-to-cycle jitter 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 28. Symbol tprog tERASE tME Flash memory characteristics Parameter Conditions Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 Unit s ms ms 16-bit programming time TA-40 to +105 C Page (1 KB) erase time Mass erase time TA -40 to +105 C TA -40 to +105 C Doc ID 13587 Rev 11 53/92 Electrical characteristics Table 28. Symbol STM32F103x8, STM32F103xB Flash memory characteristics (continued) Parameter Conditions Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V Min(1) Typ Max(1) 20 Unit mA IDD Supply current Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V 5 50 2 3.6 mA A V Vprog Programming voltage 1. Guaranteed by design, not tested in production. Table 29. Symbol Flash memory endurance and data retention Value Parameter Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 1 kcycle(2) at TA = 85 C 1 kcycle(2) at TA = 105 C 10 kcycles (2) Min(1) 10 30 10 20 Unit Typ Max kcycles NEND Endurance tRET Data retention Years at TA = 55 C 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 30. They are based on the EMS levels and classes defined in application note AN1709. 54/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 30. Symbol Electrical characteristics EMS characteristics Parameter Conditions Level/ Class 2B VFESD VDD 3.3 V, TA +25 C, Voltage limits to be applied on any I/O pin to fHCLK 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, TA +25 C, fHCLK 72 MHz conforms to IEC 61000-4-4 VEFTB 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 31. Symbol EMI characteristics Parameter Conditions Monitored frequency band 0.1 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 12 22 23 4 12 19 29 4 dBV SEMI Peak level VDD 3.3 V, TA 25 C, LQFP100 package compliant with IEC 61967-2 Doc ID 13587 Rev 11 55/92 Electrical characteristics STM32F103x8, STM32F103xB 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 32. Symbol VESD(HBM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Conditions TA +25 C conforming to JESD22-A114 TA +25 C conforming to JESD22-C101 Class 2 Maximum value(1) 2000 V II 500 Unit Electrostatic discharge VESD(CDM) voltage (charge device model) 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 33. Symbol LU Electrical sensitivities Parameter Static latch-up class Conditions TA +105 C conforming to JESD78A Class II level A 56/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 34. Symbol VIL VIH VIL VIH I/O static characteristics Parameter Input low level voltage Standard IO input high level voltage IO FT(1) input high level voltage Input low level voltage CMOS ports Input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) 0.65 VDD 200 5% VDD(3) VSS VIN VDD Standard I/Os VIN= 5 V I/O FT Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) I/O pin capacitance VIN VSS VIN VDD 30 30 40 40 5 1 A 3 50 50 k k pF TTL ports Conditions Min -0.5 2 2 -0.5 Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit Vhys IO FT Schmitt trigger voltage hysteresis(2) Ilkg Input leakage current (4) RPU RPD CIO 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: For VIH: - - if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included For VIL: - - Doc ID 13587 Rev 11 57/92 Electrical characteristics STM32F103x8, STM32F103xB Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. Symbol VOL(1) VOH(2) VOL (1) VOH (2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3) Output voltage characteristics Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 Unit IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. 58/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 24 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 36. I/O AC characteristics(1) Parameter Conditions Min Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125(3) 10 25(3) CL = 50 pF, VDD = 2 V to 3.6 V 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) ns MHz MHz MHz ns MHz ns Unit MHz MODEx[1:0] Symbol bit value(1) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time - tEXTIpw 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 24. 3. Guaranteed by design, not tested in production. Doc ID 13587 Rev 11 59/92 Electrical characteristics Figure 24. I/O AC characteristics definition STM32F103x8, STM32F103xB 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out 10% 50% 90% tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. Symbol VIL(NRST)(1) VIH(NRST)(1) Vhys(NRST) RPU VF(NRST) (1) NRST pin characteristics Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse 300 VIN VSS 30 Conditions Min -0.5 2 200 40 50 100 Typ Max 0.8 V VDD+0.5 mV k ns ns Unit VNF(NRST)(1) NRST Input not filtered pulse 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 60/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 25. Recommended NRST pin protection Electrical characteristics External reset circuit(1) NRST(2) VDD RPU Filter Internal Reset 0.1 F STM32F10xxx ai14132c 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 37. Otherwise the reset will not be taken into account by the device. 5.3.14 TIM timer characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 38. Symbol tres(TIM) TIMx(1) characteristics Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected 13.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 x 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 59.6 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. Doc ID 13587 Rev 11 61/92 Electrical characteristics STM32F103x8, STM32F103xB 5.3.15 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 39. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb I2C characteristics Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0(3) 1000 300 0.6 s 0.6 0.6 1.3 400 s s pF Max Min 1.3 s 0.6 100 0(4) 20 + 0.1Cb 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 62/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 26. I2C bus AC waveforms and measurement circuit VDD 4 .7 k I2C bus VDD 4 .7 k STM32F103xx SDA 100 SCL Electrical characteristics 100 S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 40. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 300 200 100 50 20 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 13587 Rev 11 63/92 Electrical characteristics STM32F103x8, STM32F103xB SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) SPI characteristics(1) Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle Capacitive load: C = 30 pF Slave mode Slave mode Slave mode 30 4tPCLK 2tPCLK 50 5 5 5 4 0 2 3tPCLK 10 25 5 15 2 ns 60 18 8 70 ns % Conditions Master mode Min Max 18 MHz Unit tsu(NSS)(2) NSS setup time th(NSS)(2) (2) NSS hold time Master mode, fPCLK = 36 MHz, tw(SCKH) SCK high and low time tw(SCKL)(2) presc = 4 tsu(MI) (2) tsu(SI)(2) th(MI) (2) Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Data output disable time Slave mode, fPCLK = 20 MHz Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) th(SI)(2) ta(SO)(2)(3) tdis(SO)(2)(4) tv(SO) (2)(1) Data output valid time tv(MO) (2)(1) Data output valid time th(SO)(2) th(MO)(2) 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 64/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 27. SPI timing diagram - slave mode and CPHA = 0 Electrical characteristics NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) ai14134c th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT tv(SO) MS B O UT th(SO) BI T6 OUT tdis(SO) B I T1 IN LSB IN Figure 28. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 13587 Rev 11 65/92 Electrical characteristics Figure 29. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input STM32F103x8, STM32F103xB CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time Parameter USB transceiver startup time Max 1 Unit s Symbol tSTARTUP(1) 1. Guaranteed by design, not tested in production. 66/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 43. Symbol Input levels VDD VDI(4) VCM(4) VSE(4) USB operating voltage(2) Differential input sensitivity Differential common mode range Single ended receiver threshold I(USBDP, USBDM) Includes VDI range Electrical characteristics USB DC electrical characteristics Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 0.2 0.8 1.3 3.6 V 2.5 2.0 V Output levels VOL VOH Static output level low Static output level high RL of 1.5 k to 3.6 V(5) RL of 15 k to VSS(5) 2.8 0.3 V 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers Figure 30. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines V CRS VS S tf tr ai14137 Table 44. Symbol USB: Full-speed electrical characteristics(1) Parameter Conditions Min Max Unit Driver characteristics tr tf trfm VCRS Rise time(2) Fall time (2) CL = 50 pF CL = 50 pF tr/tf 4 4 90 1.3 20 20 110 2.0 ns ns % V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.16 CAN (controller area network) interface Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). Doc ID 13587 Rev 11 67/92 Electrical characteristics STM32F103x8, STM32F103xB 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: Table 45. Symbol VDDA VREF+ IVREF fADC fS(2) fTRIG(2) VAIN(3) RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2) It is recommended to perform a calibration after each power-up. ADC characteristics Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency fADC = 14 MHz 0.6 0.05 Conditions Min 2.4 2.4 160(1) Typ Max 3.6 VDDA 220(1) 14 1 823 17 Conversion voltage range External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 14 MHz fADC = 14 MHz 5.9 83 fADC = 14 MHz 0.214 3 fADC = 14 MHz (4) Unit V V A MHz MHz kHz 1/fADC V k k pF s 1/fADC s 1/fADC s 1/fADC s 1/fADC s s 1/fADC 0 (VSSA or VREFtied to ground) See Equation 1 and Table 46 for details VREF+ 50 1 8 0.143 2 (4) fADC = 14 MHz 0.107 1.5 0 1 0 17.1 239.5 1 18 14 to 252 (tS for sampling +12.5 for successive approximation) 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA), see Table 5 and Figure 6. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45. 68/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Equation 1: RAIN max formula: TS R AIN ------------------------------------------------------------- - R ADC N+2 f ADC C ADC ln 2 Electrical characteristics The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 46. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (s) 0.11 0.54 0.96 2.04 2.96 3.96 5.11 17.1 0.4 5.9 11.4 25.2 37.2 50 NA NA RAIN max (k) 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Based on characterization, not tested in production. Table 47. Symbol ET EO EG ED EL ADC accuracy - limited test conditions(1) (2) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration Typ 1.3 1 0.5 0.7 0.8 Max(3) 2 1.5 1.5 1 1.5 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. Doc ID 13587 Rev 11 69/92 Electrical characteristics Table 48. Symbol ET EO EG ED EL STM32F103x8, STM32F103xB ADC accuracy(1) (2) (3) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Test conditions Typ 2 1.5 1.5 1 1.5 Max(4) 5 2.5 3 2 3 LSB Unit 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. 4. Based on characterization, not tested in production. Figure 31. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 5 6 7 4093 4094 4095 4096 VDDA ai14395b 70/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Figure 32. Typical connection diagram using the ADC VDD VT 0.6 V AINx Cparasitic VT 0.6 V IL1 A Electrical characteristics RAIN(1) STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) VAIN ai14150c 1. Refer to Table 45 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 33 or Figure 34, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 33. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 F // 10 nF VDDA 1 F // 10 nF VSSA /VREF- (see note 1) ai14388b 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 13587 Rev 11 71/92 Electrical characteristics STM32F103x8, STM32F103xB Figure 34. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai14389 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.18 Temperature sensor characteristics Table 49. Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25 C Startup time ADC sampling time when reading the temperature 4.0 1.34 4 Min Typ Max Unit C mV/C V s s 1 4.3 1.43 2 4.6 1.52 10 17.1 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 72/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics 6 6.1 Package characteristics Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 13587 Rev 11 73/92 Package characteristics STM32F103x8, STM32F103xB Figure 35. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Seating plane C A2 A ddd C Figure 36. Recommended footprint (dimensions in mm)(1)(2)(3) 4.30 1.00 27 19 A3 E2 b 27 19 A1 28 18 4.10 0.50 28 18 4.30 4.80 4.10 4.80 e D D2 36 10 0.75 1 9 36 0.30 10 1 E 9 L ZR_ME 6.30 ai14870b Pin # 1 ID R = 0.20 1. Drawing is not to scale. 2. The back-side pad is not internally connected to the VSS or VDD power pads. 3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should also be soldered to the PCB. It is recommended to connect it to VSS. Table 50. Symbol VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data millimeters Min Typ 0.900 0.020 0.650 0.250 0.180 5.875 1.750 5.875 1.750 0.450 0.350 0.230 6.000 3.700 6.000 3.700 0.500 0.550 0.080 0.300 6.125 4.250 6.125 4.250 0.550 0.750 0.0071 0.2313 0.0689 0.2313 0.0689 0.0177 0.0138 Max 1.000 0.050 1.000 Min 0.0315 inches(1) Typ 0.0354 0.0008 0.0256 0.0098 0.0091 0.2362 0.1457 0.2362 0.1457 0.0197 0.0217 0.0031 0.0118 0.2411 0.1673 0.2411 0.1673 0.0217 0.0295 Max 0.0394 0.0020 0.0394 A A1 A2 A3 b D D2 E E2 e L ddd 0.800 1. Values in inches are converted from mm and rounded to 4 decimal digits. 74/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics Figure 37. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 51. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches(1) Max 1.700 0.270 1.085 0.30 0.80 0.45 9.85 0.50 10.00 7.20 9.85 10.00 7.20 0.80 1.40 0.12 0.15 0.08 100 10.15 0.3878 0.55 10.15 0.0177 0.3878 0.0197 0.3937 0.2835 0.3937 0.2835 0.0315 0.0551 0.0047 0.0059 0.0031 0.3996 0.0106 0.0427 0.0118 0.0315 0.0217 0.3996 Min Typ Max 0.0669 Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff N (number of balls) Typ 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 11 75/92 Package characteristics STM32F103x8, STM32F103xB Figure 38. Recommended PCB design rules (0.80/0.75 mm pitch BGA) 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print Dpad Dsm Dpad 76/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics Figure 40. Recommended footprint(1)(2) Figure 39. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k D D1 D3 75 76 51 75 51 L L1 C 76 0.5 50 0.3 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 25 25 12.3 Pin 1 1 identification e ccc C 16.7 A1 A2 A SEATING PLANE C 1L_ME ai14906 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 52. Symbol LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.6 0.05 1.35 0.17 0.09 15.8 13.8 16 14 12 15.8 13.8 16 14 12 0.5 0.45 0.6 1 0.0 3.5 0.08 7.0 0.0 0.75 0.0177 16.2 14.2 0.622 0.5433 1.4 0.22 0.15 1.45 0.27 0.2 16.2 14.2 0.002 0.0531 0.0067 0.0035 0.622 0.5433 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0197 0.0236 0.0394 3.5 0.0031 7.0 0.0295 0.6378 0.5591 0.0551 0.0087 Min inches(1) Typ Max 0.063 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 11 77/92 Package characteristics STM32F103x8, STM32F103xB Figure 41. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline(1) A A2 Figure 42. Recommended footprint(1)(2) 48 33 0.3 A1 49 0.5 32 E E1 b 12.7 10.3 e 10.3 64 17 1.2 1 7.8 16 D1 D L1 c 12.7 ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53. Symbol LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 A A1 A2 b c D D1 E E1 e L L1 N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 78/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics Figure 43. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline B A A1 e D D1 A F H G F E E1 D C B A e 1 A3 A4 A2 Seating C plane Bottom view ME_R8 F E 2 3 4 5 6 7 8 A1 ball pad corner Ob (64 balls) 1. Drawing is not to scale. Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data millimeters inches(1) Max 1.200 0.150 0.785 0.200 0.600 0.250 4.850 0.300 5.000 3.500 4.850 5.000 3.500 0.500 0.750 0.080 0.150 0.050 5.150 0.1909 0.350 5.150 0.0098 0.1909 0.0118 0.1969 0.1378 0.1969 0.1378 0.0197 0.0295 0.0031 0.0059 0.0020 0.2028 0.0059 0.0309 0.0079 0.0236 0.0138 0.2028 Min Typ Max 0.0472 Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Typ 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 11 79/92 Package characteristics STM32F103x8, STM32F103xB Figure 44. Recommended PCB design rules for pads (0.5 mm pitch BGA) Pitch D pad Dsm 0.5 mm 0.27 mm 0.35 mm typ (depends on the soldermask registration tolerance) 0.27 mm aperture diameter Solder paste Dpad Dsm ai15495 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process 80/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics Figure 45. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline(1) Seating plane C Figure 46. Recommended footprint(1)(2) A A2 A1 ccc b C D D1 k D3 36 25 L1 7.30 37 c 0.25 mm Gage plane 36 0.50 1.20 25 24 0.30 A1 L 9.70 5.80 7.30 0.20 37 24 48 1 13 12 1.20 5.80 E3 E1 E 9.70 ai14911b 48 Pin 1 identification 1 12 13 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 55. Symbol LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.600 0.050 1.350 0.170 0.090 8.800 6.800 9.000 7.000 5.500 8.800 6.800 9.000 7.000 5.500 0.500 0.450 0.600 1.000 0 3.5 0.080 7 0 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.220 0.150 1.450 0.270 0.200 9.200 7.200 0.0020 0.0531 0.0067 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3543 0.2756 0.2165 0.0197 0.0236 0.0394 3.5 0.0031 7 0.0295 0.3622 0.2835 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 13587 Rev 11 81/92 Package characteristics STM32F103x8, STM32F103xB 6.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 35. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 56. Symbol Package thermal characteristics Parameter Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.8 mm pitch Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient TFBGA64 - 5 x 5 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch Value 44 46 45 C/W 65 55 18 Unit JA 6.2.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 82/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Package characteristics 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 57: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 56 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 82 C + (46 C/W x 447 mW) = 82 C + 20.6 C = 102.6 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 57: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 13587 Rev 11 83/92 Package characteristics STM32F103x8, STM32F103xB Using the values obtained in Table 56 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 57: Ordering information scheme). Figure 47. LQFP100 PD max vs. TA 700 600 PD (mW) 500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7 TA (C) 84/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Ordering information scheme 7 Ordering information scheme Table 57. Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count T = 36 pins C = 48 pins R = 64 pins V = 100 pins Flash memory size(1) 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and real 1. Although STM32F103x6 devices are not described in this datasheet, orderable part numbers that do not show the A internal code after temperature range code 6 or 7 should be referred to this datasheet for the electrical characteristics. The low-density datasheet only covers STM32F103x6 devices that feature the A code. Ordering information scheme STM32 F 103 C 8 T 7 xxx For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 13587 Rev 11 85/92 Revision history STM32F103x8, STM32F103xB 8 Revision history Table 58. Date 01-jun-2007 Document revision history Revision 1 Initial release. Flash memory size modified in Note 8, Note 5, Note 7, Note 9 and BGA100 pins added to Table 5: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line LFBGA100 ballout added. THSE changed to TLSE in Figure 21: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes. tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator characteristics. IDD(HSI) max value added to Table 24: HSI oscillator characteristics. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latch-up. 25 C and 85 C conditions removed and class name modified in Table 33: Electrical sensitivities. RPU and RPD min and max values added to Table 34: I/O static characteristics. RPU min and max values added to Table 37: NRST pin characteristics. Figure 26: I2C bus AC waveforms and measurement circuit and Figure 25: Recommended NRST pin protection corrected. Notes removed below Table 9, Table 37, Table 43. IDD typical values changed in Table 11: Maximum current consumption in Run and Sleep modes. Table 38: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 45: ADC characteristics. In Table 29: Flash memory endurance and data retention, typical endurance and data retention for TA = 85 C added, data retention for TA = 25 C removed. VBG changed to VREFINT in Table 12: Embedded internal reference voltage. Document title changed. Controller area network (CAN) section modified. Figure 12: Power supply scheme modified. Features on page 1 list optimized. Small text changes. Changes 20-Jul-2007 2 86/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 58. Date Revision history Document revision history (continued) Revision Changes STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see Section 6: Package characteristics). All packages are ECOPACK(R) compliant. Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package characteristics). Table 5: Medium-density STM32F103xx pin definitions updated and clarified. Table 26: Low-power mode wakeup timings updated. TA min corrected in Table 12: Embedded internal reference voltage. Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics. VESD(CDM) value added to Table 32: ESD absolute maximum ratings. Note 3 added and VOH parameter description modified in Table 35: Output voltage characteristics. Note 1 modified under Table 36: I/O AC characteristics. Equation 1 and Table 46: RAIN max for fADC = 14 MHz added to Section 5.3.17: 12-bit ADC characteristics. VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified and tlatr added in Table 45: ADC characteristics. Figure 31: ADC accuracy characteristics updated. Note 1 modified below Figure 32: Typical connection diagram using the ADC. Electrostatic discharge (ESD) on page 56 modified. Number of TIM4 channels modified in Figure 1: STM32F103xx performance line block diagram. Maximum current consumption Table 13, Table 14 and Table 15 updated. Vhysmodified in Table 34: I/O static characteristics. Table 48: ADC accuracy updated. tVDD modified in Table 10: Operating conditions at power-up / power-down. VFESD value added in Table 30: EMS characteristics. Values corrected, note 2 modified and note 3 removed in Table 26: Low-power mode wakeup timings. Table 16: Typical and maximum current consumptions in Stop and Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2 modified, Note 2 added. Table 21: Typical current consumption in Standby mode added. On-chip peripheral current consumption on page 47 added. ACCHSI values updated in Table 24: HSI oscillator characteristics. Vprog added to Table 28: Flash memory characteristics. Upper option byte address modified in Figure 9: Memory map. Typical fLSI value added in Table 25: LSI oscillator characteristics and internal RC value corrected from 32 to 40 kHz in entire document. TS_temp added to Table 49: TS characteristics. NEND modified in Table 29: Flash memory endurance and data retention. TS_vrefint added to Table 12: Embedded internal reference voltage. Handling of unused pins specified in General input/output characteristics on page 57. All I/Os are CMOS and TTL compliant. Figure 33: Power supply and reference decoupling (VREF+ not connected to VDDA) modified. tJITTER and fVCO removed from Table 27: PLL characteristics. Appendix A: Important notes on page 81 added. Added Figure 14, Figure 15, Figure 17 and Figure 19. 18-Oct-2007 3 Doc ID 13587 Rev 11 87/92 Revision history Table 58. Date STM32F103x8, STM32F103xB Document revision history (continued) Revision Changes Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 13 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: STM32F103xx mediumdensity device features and peripheral counts. Main function and default alternate function modified for PC14 and PC15 in, Note 6 added and Remap column added in Table 5: Mediumdensity STM32F103xx pin definitions. VDD-VSS ratings and Note 1 modified in Table 6: Voltage characteristics, Note 1 modified in Table 7: Current characteristics. Note 1 and Note 2 added in Table 11: Embedded reset and power control block characteristics. IDD value at 72 MHz with peripherals enabled modified in Table 14: Maximum current consumption in Run mode, code with data processing running from RAM. IDD value at 72 MHz with peripherals enabled modified in Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM on page 41. IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Note added in Table 17 on page 45 and Table 18 on page 46. ADC1 and ADC2 consumption and notes modified in Table 19: Peripheral current consumption. tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23, respectively. Maximum values removed from Table 26: Low-power mode wakeup timings. tRET conditions modified in Table 29: Flash memory endurance and data retention. Figure 12: Power supply scheme corrected. Figure 18: Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added. Note removed below Figure 27: SPI timing diagram - slave mode and CPHA = 0. Note added below Figure 28: SPI timing diagram - slave mode and CPHA = 1(1). Details on unused pins removed from General input/output characteristics on page 57. Table 41: SPI characteristics updated. Table 42: USB startup time added. VAIN, tlat and tlatr modified, note added and Ilkg removed in Table 45: ADC characteristics. Test conditions modified and note added in Table 48: ADC accuracy. Note added below Table 46 and Table 49. Inch values corrected in Table 52: LQPF100, 14 x 14 mm 100-pin lowprofile quad flat package mechanical data, Table 53: LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data and Table 55: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data. JAvalue for VFQFPN36 package added in Table 56: Package thermal characteristics Order codes replaced by Section 7: Ordering information scheme. MCU `s operating conditions modified in Typical current consumption on page 44. Avg_Slope and V25 modified in Table 49: TS characteristics. I2C interface characteristics on page 62 modified. Impedance size specified in A.4: Voltage glitch on ADC input 0 on page 81. 22-Nov-2007 4 88/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 58. Date Revision history Document revision history (continued) Revision Changes Figure 2: Clock tree on page 20 added. Maximum TJ value given in Table 8: Thermal characteristics on page 35. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 9: Memory map on page 31 for address). IDD modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. ACCHSI modified in Table 24: HSI oscillator characteristics on page 52, note 2 removed. PD, TA and TJ added, tprog values modified and tprog description clarified in Table 28: Flash memory characteristics on page 53. tRET modified in Table 29: Flash memory endurance and data retention. VNF(NRST) unit corrected in Table 37: NRST pin characteristics on page 60. Table 41: SPI characteristics on page 64 modified. IVREF added to Table 45: ADC characteristics on page 68. Table 47: ADC accuracy - limited test conditions added. Table 48: ADC accuracy modified. LQFP100 package specifications updated (see Section 6: Package characteristics on page 73). Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36 footprints added (see Figure 40, Figure 42, Figure 46 and Figure 36). Section 6.2: Thermal characteristics on page 82 modified, Section 6.2.1 and Section 6.2.2 added. Appendix A: Important notes on page 81 removed. Small text changes. Figure 9: Memory map clarified. In Table 29: Flash memory endurance and data retention: - NEND tested over the whole temperature range - cycling conditions specified for tRET - tRET min modified at TA = 55 C V25, Avg_Slope and TL modified in Table 49: TS characteristics. CRC feature removed. CRC feature added back. Small text changes. Section 1: Introduction modified. Section 2.2: Full compatibility throughout the family added. IDD at TA max = 105 C added to Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 42. IDD_VBAT removed from Table 21: Typical current consumption in Standby mode on page 47. Values added to Table 40: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) on page 63. Figure 27: SPI timing diagram - slave mode and CPHA = 0 on page 65 modified. Equation 1 corrected. tRET at TA = 105 C modified in Table 29: Flash memory endurance and data retention on page 54. VUSB added to Table 43: USB DC electrical characteristics on page 67. Figure 47: LQFP100 PD max vs. TA on page 84 modified. Axx option added to Table 57: Ordering information scheme on page 85. 14-Mar-2008 5 21-Mar-2008 6 22-May-2008 7 Doc ID 13587 Rev 11 89/92 Revision history Table 58. Date STM32F103x8, STM32F103xB Document revision history (continued) Revision Changes Power supply supervisor updated and VDDA added to Table 9: General operating conditions. Capacitance modified in Figure 12: Power supply scheme on page 33. Table notes revised in Section 5: Electrical characteristics. Table 16: Typical and maximum current consumptions in Stop and Standby modes modified. Data added to Table 16: Typical and maximum current consumptions in Stop and Standby modes and Table 21: Typical current consumption in Standby mode removed. fHSE_ext modified in Table 20: High-speed external user clock characteristics on page 48. fPLL_IN modified in Table 27: PLL characteristics on page 53. Minimum SDA and SCL fall time value for Fast mode removed from Table 39: I2C characteristics on page 62, note 1 modified. th(NSS) modified in Table 41: SPI characteristics on page 64 and Figure 27: SPI timing diagram - slave mode and CPHA = 0 on page 65. CADC modified in Table 45: ADC characteristics on page 68 and Figure 32: Typical connection diagram using the ADC modified. Typical TS_temp value removed from Table 49: TS characteristics on page 72. LQFP48 package specifications updated (see Table 55 and Table 46), Section 6: Package characteristics revised. Axx option removed from Table 57: Ordering information scheme on page 85. Small text changes. STM32F103x6 part numbers removed (see Table 57: Ordering information scheme). Small text changes. General-purpose timers (TIMx) and Advanced-control timer (TIM1) on page 15 updated. Notes updated in Table 5: Medium-density STM32F103xx pin definitions on page 26. Note 2 modified below Table 6: Voltage characteristics on page 34, |VDDx| min and |VDDx| min removed. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 38. IDD in standby mode at 85 C modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 42. General input/output characteristics on page 57 modified. fHCLK conditions modified in Table 30: EMS characteristics on page 55. JA and pitch value modified for LFBGA100 package in Table 56: Package thermal characteristics. Small text changes. 21-Jul-2008 8 22-Sep-2008 9 90/92 Doc ID 13587 Rev 11 STM32F103x8, STM32F103xB Table 58. Date Revision history Document revision history (continued) Revision Changes I/O information clarified on page 1. Figure 3: STM32F103xx performance line LFBGA100 ballout modified. Figure 9: Memory map modified. Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column in Table 5: Medium-density STM32F103xx pin definitions. PD for LFBGA100 corrected in Table 9: General operating conditions. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Figure 18 shows a typical curve (title modified). ACCHSI max values modified in Table 24: HSI oscillator characteristics. TFBGA64 package added (see Table 54 and Table 43). Small text changes. Note 5 updated and Note 4 added in Table 5: Medium-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. IDD_VBAT value added to Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 16: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings. Note 1 modified below Figure 22: Typical application with an 8 MHz crystal. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 54. Jitter added to Table 27: PLL characteristics. Table 41: SPI characteristics modified. CADC and RAIN parameters modified in Table 45: ADC characteristics. RAIN max values modified in Table 46: RAIN max for fADC = 14 MHz. Figure 37: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline updated. 23-Apr-2009 10 22-Sep-2009 11 Doc ID 13587 Rev 11 91/92 STM32F103x8, STM32F103xB Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 92/92 Doc ID 13587 Rev 11 |
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